As the minimum feature size of integrated circuits (ICs) continues to shrink and the desire for reduced power consumption persists, the core logic section of digital circuits are being supplied from ever-decreasing voltages, such as down to 1.0 V or lower. However, the power supply voltages of other sections of the IC (e.g., the input/output (I/O) section) may remain at higher voltage levels, such as 1.8 V, 2.5 V, 3.3 V, or higher. These higher voltage levels may be used to interface with other logic types or to assure compatibility with other devices. Therefore, a voltage level shifter may be used to level shift a signal from a relatively low supply voltage to a relatively high supply voltage or vice versa.
Voltage level shifters are used in many applications as the interface between low and high voltage control or clock signals. These applications include analog-to-digital converters (ADCs), digital-to-analog converters (DACs), clock level shifters, and any other high-speed interface with multiple supply voltages. An ideal level shifter shifts the input signal to a different level and connects the two interfaces together without any issues, such that the impact of the level shifter is almost negligible. However, conventional level shifters may have high latency, inconsistent performance over various combinations of the voltage levels' extremes, and/or distorted duty cycle in high-speed interface applications.